A printed circuit board comprises a substrate, typically made of mylar whose surface has metal lines formed thereon which are electrical conductors used to connect various circuit components together and/or to external circuity. In order to keep pace with the integrated circuit industry, feature sizes, i.e., metal lines and spaces between the metal lines have shrunk to very small dimensions. While techniques for the fabrication of printed circuit boards have greatly advanced in recent years, a certain percentage still come out of production with one or more of a variety of flaws. For example, a printed circuit may have lines and/or spaces too narrow, shorts, opens, pinholes or the like, any one of which may render the board useless. Due to their extremely small sizes visual detection of such flaws in boards with very fine lines is neither technically effective nor economically practical. Thus, automation of the printed circuit board inspection process is an essential requirement in the printed circuit board manufacturing business.
A novel method for the automatic inspection of printed circuit boards is disclosed in a patent application filed on even date herewith and assigned to the same assignee as the present invention entitled "COARSE FLAW DETECTOR FOR PRINTED CIRCUIT BOARD INSPECTION" having Ser. No. 06/745,967 filed June 17, 1985. That method relates to an image matching method of inspection wherein the printed circuit board being tested is compared with a stored master to determine acceptability. In doing so, patches of the test surface made up of n.times.n picture elements, i.e., pixels are compared with corresponding patches of the stored master. If there is a mismatch between any pair of corresponding patches, a flaw is indicated.
In the invention described in the above-identified application a video camera, e.g., a CCD array is sensitized, e.g., by exposure pulses at a plurality of locations as it scans along the test surface. Each of these locations is designated a scan line. All the bits attributable to a scan line are transferred out of the CCD array in series. Each of the bits is thus representative of a pixel seen by the CCD array in a particular scan line. A unique arrangement of delay lines and shift registers convert the serial stream of bits into parallel outputs of n bits each from which other circuitry forms patches of n.times.n pixels. Each set of n bits is converted into a binary number. The binary number representative of each new set of n bits is added to the last until a binary number representative of a patch of n.times.n bits is generated. Each of these binary numbers is compared to a corresponding binary number obtained from the stored reference or master until the entire printed circuit is inspected. If one or more test patches fails to match its corresponding reference patch, a flaw is indicated.
The foregoing described printed circuit board inspection system presupposes perfect registration, i.e., each test patch is precisely registered with its corresponding reference patch. In actual practice, however, this is not usually the case. Misregistration between a test printed circuit board inspected in real time and the stored reference results from a number of causes, e.g., finite pixel resolution, errors in the positioning system and distortion of the printed circuit boards. This latter is the predominate cause of misregistration and is primarily due to stretch and shrink of the test board.
The present invention relates to a system which overcomes the above-mentioned problem of misregistration. In so doing, the present invention is not limited to the inspection system briefly described above and is applicable to inspection systems where any surface is inspected for flaws and not just printed circuit boards.